The present invention relates to a method for manufacturing a polysilicon thin-film transistor, and more particularly, to a method for forming a silicide on an offset thin-film transistor which is frequently applied to a liquid crystal display in a single body, to decease the short-channel effects of a short channel MOSFET and to reduce leakage current.
FIG. 1 is a section view of a conventional offset polysilicon thin-film transistor. The structure of the transistor shown in FIG. 1 is as follows.
A polysilicon layer 1 (active layer) is formed on the upper surface of a substrate 100. Then, a source 2 and,drain 6 region each having a dopant (n.sup.+) implanted therein are respectively formed on either side of the active layer, and a region 7 thereof (adjacent to each of the source and drain regions) is doped with a low concentration dopant (n.sup.-) in: order to decrease leakage current. A gate insulating layer 3 is formed on the upper surface of the active layer and a gate 5 is formed thereon.
A method for fabricating the offset polysilicon thin-film transistor having the above structure will be described in connection with FIG. 2.
First, a sensitie layer (photoresist) is coated over and patterned around gate 5 to form a photoresist pattern 4. Thereafter, a first ion implantation process 101, wherein a high concentration dopant (n.sup.+) is implanted, is performed for forming the source and Grain regions within the active layer. Thereafter, photoresist pattern 4 is removed and another mask (not shown) is formed. Offset regions 7 (n.sup.-) are formed by a second ion implantation process (not shown), wherein a low concentration dopant (n.sup.-), is implanted. The second mask is then removed to complete the formation of an offset polysilicon thin-film transistor.
As described above, according to the conventional method for fabricating the offset polysilicon thin-film transistor, a photoresist pattern is formed to mask the offset regions and then the ion-implantation is performed. Here, the thickness of the photoresist, that is, the masking material, is always greater than 1 .mu.m; here, about 1.2 .mu.m. Thus, a width l of offset regions 7 is over 1 .mu.m. Also, since the photoresist may be unevenly formed on either side of gate 5 during the coating process and the pattern-etching process after coating, the offset regions have an asymmetrical structure which causes undesirable changes the electrical characteristics of the device compared with a symmetrical structure formation.